Process variation tolerant bank collision detection circuit

ABSTRACT

A process variation tolerant collision detection apparatus for use in detecting collisions in a multibank memory. The apparatus may receive a plurality of memory commands for execution at the multibank memory. The plurality of memory commands may be compared by an index address comparator and a bank address comparator to generate an index match signal and a bank match signal. The index match signal and the bank match signal may be analyzed by a timing correction module such that errors associated with process variation of the signals used in the system may be eliminated. Accordingly, a corrected index match signal and a corrected bank match signal may be provided to a collision detection circuit to determine whether a collision exits.

BACKGROUND

In computing environments, memory is employed to store data for use in,or resulting from execution of, computations associated with computingfunctionality of the computing environment. The speed and accuracy withwhich data may be written to and read from memory may be a limitingfactor regarding the speed at which a computing environment may beexecuted. In this regard, it may be appreciated that the ability toaccurately and rapidly write data to and read data from a memory mayimprove the speed at which the computing environment may be executedand, thus, improve the computing efficiency of the computingenvironment.

One example of particular type of memory that may assist in the rapidexecution of read and write functionality with respect to a memoryincludes a multibank memory. A multibank memory includes a plurality ofmemory banks, each having a plurality of indexes corresponding to memorylocations at which data may be stored. In this regard, multibank memorymay be useful because independent memory commands (e.g., write and/orread commands) may be addressed to, and carried out with respect to,different respective ones of the plurality of memory bankssimultaneously, thus improving the speed and efficiency of the memory.

However, in the use of a multibank memory, a condition may exist wherememory commands addressed to the multibank memory may not be properlyexecuted in the memory. These conditions may be referred to as acollision. For example, where more than one memory command is addressedto different indexes in the same memory bank, the memory commands may benot able to be executed, and a collision may occur should the memorycommands be attempted. Accordingly, absent a mechanism to detect thepotential collision, execution of colliding memory commands may resultin false reads, false writes, corrupted memory, or other problems thatmay detract from the accuracy and speed from which, or to which, thememory may be read or written. Accordingly, detection of data collisionsmay be desirable by way of scrutinizing memory commands to detect theoccurrence of a data collision.

SUMMARY

In view of the foregoing, the present disclosure is generally directedto an apparatus for a memory bank collision detection circuit. Inparticularly, the present disclosure presents embodiments that may betolerant to process variations associated with signals used by theapparatus to determine a collision. Such process variation may result insignals used by a detection circuit to falsely indicate a collisionexists. For instance, process variation may be associated withvariations with respect to tolerances in the manufacturing process ofhardware used to generate and/or process signals in a computingenvironment. Other factors may also contribute to process variationincluding, for example, skewed signals, a different number of gatesemployed relative to different signals, or other factors that result insignals being offset or misaligned. However, the embodiments disclosedherein may facilitate compensation or correction mechanisms used todetect collisions while avoiding false detection situations attributableonly to process variations. Accordingly, an apparatus for fast, accuratewriting to and reading from a multibank memory may be facilitated thatreduces the potential for false data collisions detection due to processvariations.

In this regard, a first aspect described herein includes an apparatusfor collision detection in a multibank memory with protection from falsecollision detection resulting from process variation. The apparatusincludes a memory bank address comparator for receiving bank addressdata corresponding to a first memory command and a second memorycommand. The memory bank address comparator is operable to output a bankmatch signal indicative of the first memory command and the secondmemory command being directed to a common memory bank address. Theapparatus further includes a memory index address comparator forreceiving index address data corresponding to the first memory commandand the second memory command. The memory index address comparator isoperable to output an index match signal indicative of the first memorycommand and the second memory command being directed to a common memoryindex address. The apparatus further includes a collision detectioncircuit comprising a timing correction module that is operable toreceive the bank match signal and the index match signal and generate atleast one of a corrected bank match signal or a corrected index matchsignal in response to a change detected in one of the index match signalor bank match signal attributable to process variation. The collisiondetection circuit is also operable to compare the at least one of thecorrected bank match signal or the corrected index match signal togenerate a collision detection signal indicative of a collision in themultibank memory resulting from the execution of the first memorycommand and the second memory command.

A number of feature refinements and additional features are applicableto the first aspect. These feature refinements and additional featuresmay be used individually or in any combination. As such, each of thefollowing features that will be discussed may be, but are not requiredto be, used with any other feature or combination of features of thefirst aspect.

For example, in an embodiment, at least one of the bank match signal orthe index match signal may include process variation resulting in anoffset between the bank match signal and the index match signal.Accordingly, the offset may results in the false detection of acollision. Furthermore, the at least one of the corrected bank matchsignal or the corrected index match signal may reflect a state of acorresponding one of the bank match signal or the index match signalwithout the process variation. The process variation may be detectedbased on a comparison of at least two of the bank match signal, thecorrected index match signal, the first memory command, and the secondmemory command.

In an application, at least one of the corrected bank match signal orthe corrected index match signal is at least partially based on a changein a corresponding one of the index match signal or the bank matchsignal without detection of a corresponding change in at least one ofthe first memory command, the second memory command or the other of theindex match signal or bank match signal. The change in the correspondingone of the index match signal or the bank match signal attributable toprocess variation is not reflected in the at least one of the correctedbank match signal or the index match signal. The offset may result fromat least one of the bank match signal or the index match signal varyingfrom a first value to a second value without a corresponding variationin at least one of the first memory command, the second memory commandor the other of the index match signal or the bank match signal.

In an embodiment, the at least one corrected bank match signal or thecorrected index match signal may be different than a corresponding oneof the bank match signal or the index match signal, respectively.Furthermore, the index match signal may vary from the first value to thesecond value. In turn, the timing correction module may be operable tomaintain the corrected index match signal at the first value at leastuntil a corresponding change in at least one of the first memorycommand, the second memory command, or the other of the index matchsignal or the bank match signal.

In an embodiment, the first memory command may include a read commandand the second memory command comprises a write command. As such, thefirst memory command and the second memory command may result in abypass condition. In an embodiment, the execution of the first memorycommand and the second memory command may be prevented in response tothe collision detection signal generated by the collision detectioncircuit. As such, the collision detection signal may be communicated tothe multibank memory.

A second aspect described herein includes a method for detection of acollision. The method includes receiving a first memory command havingan address comprising a first bank address and a first index address anda second memory command having an address comprising a second bankaddress and a second index address. The method also includes comparingthe first bank address with the second bank address to generate a bankmatch signal indicative of whether the first bank address and the secondbank address are the same. Additionally, the method includes evaluatingthe first index address with the second index address to generate anindex match signal indicative of whether the first index address and thesecond index address are the same. The method also includes detecting achange in one of the bank match signal or the index match signalresulting from process variation and generating at least one of acorrected bank match signal or a corrected index match signal inresponse to the detecting. The method may also include outputting, inresponse to the maintaining, a collision detection signal based on theat least one of the corrected bank match signal or the corrected indexmatch signal.

A number of feature refinements and additional features are applicableto the second aspect. These feature refinements and additional featuresmay be used individually or in any combination. As such, each of thefollowing features that will be discussed may be, but are not requiredto be, used with any other feature or combination of features of thesecond aspect.

For example, in an embodiment, the generating may include maintainingthe corrected index match signal constant in response to a change in theindex match signal so long as the bank match signal is constant. Themaintaining may be interrupted upon a change in the bank match signal,or the maintaining may be interrupted by a detected change in at leastone of the first memory command or the second memory command. In anembodiment, the collision detection signal may be indicative of acollision when a comparison of at least one of the corrected bank matchsignal or the corrected index match signal indicates the first bankaddress and the second bank address are the same and the first indexaddress and the second index address are different. In an embodiment,the bank match signal and the index match signal may indicate a bypasscondition prior to the change.

In an embodiment, the method may also include preventing execution ofthe first memory command and the second memory command when thecollision detection signal indicates a collision.

A third aspect described herein includes an apparatus for collisiondetection with protection for process tolerance variations. Theapparatus includes a comparison means for comparing a first memorycommand and a second memory command to generate a bank match signalindicative of whether the first memory command was addressed to a commonbank address as the second memory command and to generate an index matchsignal indicative of whether the first memory command was addressed to acommon index address as the second memory command. The apparatus alsoincludes a timing correction means for generating at least one correctedsignal. The at least one corrected signal corresponds to a correction ofat least one of the bank match signal or the index match signal inresponse to a detected process variation. The apparatus further includesa collision detection means for analyzing the corrected collisiondetection signal relative to at least one of the bank match signal orthe index match signal to determine a collision.

The present invention is directed to the embodiments and aspects thatare summarized above, alone or in any combination, as well as additionalembodiments and aspects and combinations thereof that will be apparentfrom the following description of the invention. However, the foregoingsummary is intended to provide a basic understanding of at least someembodiments and aspects of the invention. This summary is not anextensive overview of the invention and is not intended to identify keyor critical elements of the invention or to delineate the scope of theinvention. The foregoing summary merely presents some concepts of theinvention in general form as a prelude to a more detailed descriptionprovided below.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 depicts a schematic view of an embodiment of a computingenvironment including a multibank memory structure.

FIG. 2 depicts a schematic view of an embodiment of an apparatus forprocess variation tolerant collision detection.

FIG. 3 depicts a plurality of signal waveforms corresponding to thesystem FIG. 2 when a collision is detected.

FIG. 4 depicts a plurality of signal waveforms correspond to the systemof FIG. 2 corresponding to a bypass condition.

FIG. 5 depicts a plurality of signal waveforms corresponding to thesystem of FIG. 2 with variations resulting from process variations.

FIG. 6 depicts a plurality of signal waveforms correspond to the systemof FIG. 2 wherein embodiment of the apparatus for bank collisiondetection with process tolerance variations has been applied to thesignal waveforms.

DETAILED DESCRIPTION

The following description is not intended to limit the invention to theforms disclosed herein. Consequently, variations and modificationscommensurate with the following teachings, skill and knowledge of therelevant art are within the scope of the present invention. Theembodiments described herein are further intended to explain modes knownof practicing the invention and to enable others skilled in the art toutilize the invention in such, or other embodiments and with variousmodifications required by the particular applications(s) or use(s) ofthe present invention.

With reference to FIG. 1, an embodiment of a computing environment 10including a multibank memory storage device 14 is depicted. The memory14 may be in operative communication with a processor 12. The processor12 may be operable to address memory commands (e.g., read and/or writecommands) to the memory 14. The memory commands may be addressed suchthat each command references a location in the memory 14 to which thememory command is targeted. In this regard, the memory 14 may include afirst memory bank 16 having a plurality of index addresses 20corresponding to various discrete locations in the first memory bank 16.The memory 14 may also include a second memory bank 18 having aplurality of index addresses 22 corresponding to various discretelocations in the second memory bank 18. In this regard, the processor 12may address each memory command to a particular a bank address as wellas an index address such that the location corresponding to the memorycommand may be identified in the memory 14, and the memory command maybe performed with respect to the location. In this regard, a readrequest or a write request may include address data including an indexaddress and a bank address to which the read request or write request isaddressed.

It may be appreciated that allowing for simultaneous read and/or writecommands to be addressed to different addresses in the memory 14 mayallow for increased efficiency for the memory 14. In this regard, thespeed at which data may be written to or read from memory 14 may beincreased. For example, the processor 12 may be able to communicate afirst memory command to an index address 20 in the first memory bank 16at the same time that a second memory command is communicated to anindex address 22 in the second memory bank 18.

However, as discussed above, the use of a multibank memory 14 may alsopresent the possibility of a collision. For example, when differentmemory commands are addressed to different index addresses within thesame memory bank, a collision may occur that prevents the memorycommands from being carried out with respect to the memory 14. Thecollision may occur due to limited data paths associated with eachmemory bank such that simultaneous operation in each bank is notpossible. In the event the collision is not detected, false reads, falsewrites, corruption of the memory, or other problems that may detractfrom the speed or accuracy of the memory 14 may occur.

In this regard, the memory 14 may include or be linked to a apparatus100 to detect a collision in a manner that will be described in greaterdetail below. Generally, a collision detection circuit may scrutinizememory commands to determine whether a collision exists, and thecollision detection circuit may generate a collision detection signalthat is used to prevent the memory commands from being executed should acollision be detected. For example, as described above, a collision maybe detected when memory commands are addressed to different indexes inthe same bank. However, two memory commands addressed to different banksmay not result in a collision. Furthermore, two memory commandsaddressed to the same index in the same bank may result in a bypasscondition which does not represent a collision.

In the bypass condition, the write command may result in the memorylocation at an index address in a bank being written with data and thatnewly written data subsequently being read from the memory location. Inthis regard, a write command addressed to a particular memory locationand a read command addressed to the same location may be executedwithout a collision. Accordingly, while more than one command may bedirected to the same bank, the fact that commands are addressed to thesame index may allow for the write and read commands to be executedwithout a collision occurring.

With further reference to FIG. 2, a schematic view of the apparatus 100for use in detecting a collision with respect to the plurality of memorycommands communicated to multibank memory 14 is depicted. The layout ofthe apparatus 100 is generally described prior to turning to specificexamples of operation of the apparatus 100 with reference to varioussignal waveform diagrams appearing in FIGS. 3-6.

The apparatus 100 may be operable to receive a read request 116 and awrite request 118 (e.g., from processor 12 not shown in FIG. 2). In thisregard, as described above each of the read request 116 and the writerequest 118 may include address data corresponding to a bank address andan index address to which the respective request is addressed. That is,the read request 116 may include a read index address 116 a and a readbank address 116 b. The write request 118 may include a write indexaddress 118 a and a write bank address 118 b.

Accordingly, the read index address 116 a and the write index address118 a may be communicated to an index address comparator 112. Similarly,the read bank address 116 b and the write bank address 118 b may becommunicated to a bank address comparator 114. It should be noted thatwhile a read request 116 and a write request 118 are depicted anddescribed in detail herein, it may be appreciated that the memorycommands may both comprise write commands or may both comprise readcommands. The use of read command 116 and write command 118 is forillustration and is not intended to be limiting.

The index address comparator 112 may be operable to analyze indexaddresses 116 a and 118 a to determine if the read request 116 and thewrite request 118 are addressed to a common index address. In the eventthe read request 116 and the write request 118 are addressed to a commonindex address, the index address comparator 112 may output an indexmatch signal 122 indicative of the fact the read request 116 and a writerequest 118 are addressed to a common index address. For example, if theread request 116 and the write request 118 are addressed to a commonindex address, the index match signal may be high, whereas if the readrequest 116 and the write request 118 are addressed to different indexaddresses, the index match signal may be low as will be appreciated withfurther reference to the signal waveforms in FIGS. 3-6 discussed below.

The bank address comparator 114 may similarly be operable to analyze thebank addresses 116 b and 118 b to determine if the read request 116 andthe write request 118 are addressed to a common bank address. In theevent that the read request 116 and the write request 118 are addressedto the common bank address, the bank address comparator 114 may output abank match signal 124 indicative of that fact. For example, if the readrequest 116 and the write request 118 addressed a common bank address,the index match signal 124 may be high, whereas if the requests areaddressed to different banks, the index match signal 124 may be low.

Accordingly, a collision detection circuit 130 may scrutinize the indexmatch signal 122 and the bank match signal 124 to determine whether theread request 116 and the write request 118 represent a collision.However, as may be appreciated below, the index match signal 122 and thebank match signal 124 may be subject to error due to process variation(e.g., resulting from non-ideal characteristics of hardware used in thecomputing environment 100). In this regard, comparison of the indexmatch signal 122 and the bank match signal 124 may introduce thepotential that a false collision is detected. As will become clearbelow, the false collision may be the result exclusively of processvariation present in the signals.

Accordingly, as depicted in FIG. 2, the index address comparator 112 andthe bank address comparator 114 may be operable to provide the indexmatch signal 122 and the bank match signal 124, respectively, to acollision detection circuit 200 that may include a timing correctionmodule 120 and a signal comparison module 130. The signal comparisonmodule 130 may also include a static signal generator used to generatestatic signals for use in the control of the multibank memory 14.

The timing correction module 120 may generate a corrected index matchsignal 126 and a corrected bank match signal 128 that are in turnprovided to signal comparison module 130. The corrected index matchsignal 126 and the corrected bank match signal 128 may be at least inpart based on a comparison of the index match signal 122 and the bankmatch signal 124. Additionally or alternatively, the corrected indexmatch signal 126 or the corrected bank match signal 128 may be based ona comparison of one or more of the index match signal 122, the bankmatch signal 124, the read request 116, and the write request 118. Ingeneral, the various signals provided to the timing correction module120 may be analyzed to determine anomalies in the signals attributableto process variation. In this regard, changes in the signals without acorresponding change in a complimentary signal (e.g., a change in theindex match signal 122 without a corresponding change in any one or moreof the read request 116, the write request 118, or the bank match signal124) may indicate a change in a signal results only from processvariation.

In this regard, and as will be discussed in greater detail below, thecorrected index match signal 126 and the corrected bank match signal 128may be conditioned to remove false signal values resulting solely fromprocess variation. For example, process variation may be associated withany of the various hardware used in the computing environment 100. Suchvariation may be, for example, due to physical variations in hardwareused to generate and/or process the write request 118 and/or readrequest 116. Such physical variations may be due to process variationsintroduced in the manufacture of such physical hardware. Furthermore,process variation may exist due to skew in signals, a differing numberof gates utilized to generate or process a signal (e.g., resulting insignal latency), or other factors that may result in an offset of thesignal values.

Accordingly, the corrected index match signal 126 and the corrected bankmatch signal 128 may be provided to the signal comparison module 130 foranalysis to determine if a collision exists. As the corrected indexmatch signal 126 and the corrected bank match signal 128 may becorrected to remove signal artifacts attributable to process variation,the resulting analysis may be free from false collision detections dueto process variation. In this regard, the signal comparison module 130may output a collision signal 132 to the memory 14 that is indicative ofwhether the write request 118 and the read request 116 represent acollision. In the event the collision signal 132 indicates a collision,the read request 118 and write request 116 may be prevented from beingexecuted at the memory 14. Furthermore, the collision detection signal132 may be provided (e.g., to processor 12 not shown in FIG. 2) toindicate the intended memory commands were not executed due to adetected collision. However, if no collision is detected by the signalcomparison module 130, the read request 116 and write request 118 may beexecuted at the memory 14.

With further reference to FIG. 3, signal waveforms corresponding to thevarious signals described above in the apparatus 100 are shown toillustrate the operation of the apparatus 100. For example, FIG. 3illustrates the state of various signal waveforms of the apparatus 100corresponding to a collision scenario as described above where the readcommand 116 and the write command 118 are received that are directed todifferent indexes in the same bank. As shown, a clock signal 105 maydefine a cycle period 138 extending between consecutive rising edges ofthe clock signal denoted by dotted lines 134 and 136. Also depicted,both the write request 118 and read request 116 signals become highduring the cycle period 138 indicating both memory commands are receivedfor execution with respect to the memory 14. The index match signal 122may remain low during the cycle period 138 indicating that the indexaddress comparator 112 determines that the read request 116 and thewrite request 118 are directed to different indexes. That is, it will beunderstood that the read request 116 and the write request 118 may beaddressed to different indexes in the multi bank memory block 14 asdetermined by the index address comparator 112.

Additionally, as shown in FIG. 3, the bank match signal 124 may becomehigh (at a rising edge within the cycle period 138) indicating that thebank address comparator 114 determines the bank addresses for the readrequest 116 and write request 118 are the same. Thus, the collisiondetection circuit 130 may indicate a collision signal 132 indicative ofa collision because the read request 116 and write request 118 aredirected to different index addresses in the same bank as determinedfrom a comparison of the index match signal 122 and the bank matchsignal 124. In this regard, the collision detection circuit 200 maycommunicate a collision detection signal 132 that prevent the readrequest 116 and write request 118 from being executed at the memory 14.

As such, it may be appreciated that the collision detection circuit 200may be operable to analyze the index match signal 122 and bank matchsignal 124 to determine whether a collision occurs. It may further beappreciated that if the bank match signal 124 is low, corresponding to ascenario wherein the bank address of the read signal 116 is differentthan the bank address of the write signal 118, no collision may occur asthe addresses correspond to different banks, such that no collisionoccurs regardless of the state of the index match signal 122.

Another scenario is depicted in the signal waveforms of FIG. 4corresponding to a bypass condition described above. In a bypasscondition, a first memory command (e.g., read request 116) and a secondmemory command (e.g., write request 118) that are directed at the sameindex address in the same bank may not represent a collision such thatboth operations may be carried out on the index address in the bankwithout collision. As such, in FIG. 4 the index match signal 122 and thebank match signal 124 are both indicative that the read request 116 andwrite request 118 are both directed at the same index address and samebank address. Therefore, the collision detection circuit 200 may be ableto ascertain that no collision is detected and output a collision signal132 as shown in FIG. 4 indicating no collision exists. As such, the readrequest 116 and write request 118 may be executed at the memory 14.

However, with further reference to the signal waveforms of FIG. 5, itmay be appreciated that the signals discussed herein may be subject tovariation such that the initiation (i.e., the rising edges) andtermination (i.e., the falling edges) of the signals may not correspond.As will be appreciated with further reference to FIG. 6, the processvariation may lead to scenarios where it appears that a collision occursfor a portion of the clock cycle period 138, when in reality nocollision is present and the indicating of a collision is due only toprocess variation present in the various signals.

For example, as depicted with respect to the write request 118 in FIG.5, rather than rising edge 152 of an ideal system, the actual risingedge 154 for the write request signal 118 may occur after the idealizedrising edge 152 as shown in FIG. 5. Similarly, process variation mayexist at the falling edge of the write request 118 such that an actualfalling edge 156 may occur rather than an idealized falling edge 158 ofan ideal system as depicted in FIG. 5. Similarly, the read request 116may be subject to non-ideal variation in the signal 116 such that anactual rising edge 162 is experienced rather than idealized rising edge160. Furthermore, the falling edges of the read signal 116 may besubject to variation such that an actual falling edge 164 varies from anidealized falling edge 166 of the signal.

As may be further appreciated from FIG. 5, the potential variation ofthe read request 116 and/or write request 118 may result in situationswhere it appears a collision occurs due to the initiation and/ortermination of the signals not corresponding. That is, for instance, thewrite request 118 may terminate prior to the read request 116terminating such that it appears that a collision occurs for the cycleperiod 138, when no actual collision exists. Rather, the resultingindicated collision (e.g., as shown in collision signal value 132 a and132 b in FIG. 5) may be resultant only from an indicated collisiondetected due to the variation of read request 116 and write request 118.Furthermore, process variation may be introduced at either of the indexmatch signal 122 or the bank match signal 124. For instance, despite theread request 116 and write request 118 corresponding, due to differencein the hardware used to generate the index match signal 122 and the bankmatch signal 124, variations may exist in the index match signal 122 orbank match signal 124. It may be appreciated that the process variationintroduced in either of these signals may also result in false collisiondetection signals 132 a or 132 b being detected.

In this regard, the process variation of any of the various signals usedto detect collisions may result in false collision signals beinggenerated such as false collision signal 132 a or false collision signal132 b. While not discussed explicitly in examples herein, FIG. 5 depictsa plurality of process variations that may occur with respect to any ofthe signals used to monitor for a collision such that may processvariations may result in errors being carried through to or generated inthe index match signal 122 and bank match signal 124 shown in FIG. 5. Inthis regard, the efficiency of the apparatus 100 may be reduced due tofalse detection of collisions as memory commands may be prevented frombeing executed in the memory 14 even without an actual collision. Inthis light, the timing correction module 120 of the apparatus 100 may beoperable to compare the index match signal 122 and/or the bank matchsignal 124 with respect to others of the signals to generate thecorrected index match signal 126 and corrected bank match signal 128 toeliminate errors introduced by way of process variation. That is, thecorrected index match signal 126 and the corrected bank match signal 128may be conditioned to remove errors occurring therein due to processvariations. As such, the timing correction module 120 may prevent falsecollision signals 132 a or 132 b. For example, either of the index matchsignal 122 or bank match signal 124 may be compared to the other of theindex match signal 122 or bank match signal 124 to determine if processvariation exists. For example, if the index match signal 122 changesfrom one value to another (i.e., goes from high to low) without acorresponding change in the bank match signal 122, the change in theindex match signal 122 may be attributed to process variation.Alternatively or additionally, either or both of the memory commands(e.g., read signal 116 or write signal 118) may be analyzed upondetection of a change in either of the index match signal 122 or bankmatch signal 124 to determine if the change results from a correspondingchange in the memory commands. Absent a corresponding change in thememory commands, the change may be attributed to a process variation. Assuch, the corrected index match signal 126 and corrected bank matchsignal 128 may not include such a changed determined to be resultingfrom process variation.

For example, with further reference to FIG. 6, a scenario is depictedwhere a false collision signal 132 b may exist that is attributable onlyto process variation resulting from the index match signal 122 having afalling edge 168 offset from the falling edge 170 of the bank matchsignal 124. That is, because the index match signal 122 changes from afirst value (high) to a second value (low) prior to a correspondingchange in any of the bank match signal 124, read request 116, or writerequest 118, the index match signal 122 may falsely indicate that theread request 116 and write request 118 represent a collision. Therefore,for a first period the collision detection circuit 130 may determinethat the signals correspond to a bypass condition such that no collisionis detected. This may be indicated in the collision signal 132. However,in a second period beginning at the premature termination of the indexmatch signal 122 at falling edge 168, the collision detection circuit130 may falsely indicate a collision for a portion of the cycle period138. However, the indication of a collision may be attributable only tothe offset between the termination of the index match signal 122 and thebank match signal 124.

In this regard, the timing correction module 120 may be operable togenerate a corrected index match signal 126 that compensates for theerror introduced by the process variation. That is, the timingcorrection module 120 may be operable to compare the index match signal122 to the bank match signal 124, the read request 116, and/or the writerequest 118 to determine the change at the falling edge 168 is notgenerated from an actual change in the various signal states. As such,the change may be attributed to process variation and the correctedindex match signal 126 may maintain the value prior to the change atfalling edge 168. The corrected index match signal 126 may be maintaineduntil a corresponding change in one or more of the bank match signal124, read request 116, or write request 118 is also detected. In thisregard, as depicted in FIG. 6, for example, the corrected index matchsignal 126 with falling edge 126 a may be provided to the signalcomparison module 130. Based on the corrected index match signal 126,the signal comparison module 130 may properly determine no collisionexists such that the read request 116 and write request 118 are issuedto the memory 14.

In this regard, it may be appreciated that the timing correction module120 may be operable to maintain one or both of the index match signal122 or bank match signal 124 constant during a duration of the cycleperiod 138 despite contradictory values being received from the indexaddress comparator 112 or bank address comparator 114. In this regard,the collision detection circuit 200 may also receive the read request116 and write request 118 in order to scrutinize the read request 116and write request 118 in the generation of the corrected index matchsignal 126. As such, the timing correction module 120 may compare theread request 116 and/or write request 118 to determine when either oneof the corrected index match signal 126 or corrected bank match signal128 should remain at the constant value despite a change in one of theindex match signal 122 or bank match signal 124. For example, in FIG. 6,the timing correction module 120 may maintain the corrected index matchsignal 126 constant until the read request 116 changes at the fallingedge 116 d or the bank match signal 124 changes at falling edge 170. Inthis regard, the timing correction module 120 may maintain the correctedindex match signal 126 and/or corrected bank match signal 128 constantuntil a value of the read request 116, write request 118 changes, or theother of the bank match signal 124 or index match signal 122.

Furthermore, while discussed above with respect to a corrected indexmatch signal 126 or a corrected bank match signal 128, it may beunderstood that other signals may also be corrected to remove defectsfrom process variation by the timing correction module 120. In thisregard, process variation detected in the read request 116 or the rightrequest 118 may be detected and a corrected request signal 140corresponding to either or both the read request 116 and write request118 may be provided to the signal comparison module 130 fordetermination of a collision.

In view of the foregoing, an apparatus 100 for detection of collisionsmay be provided that reduces the potential for false collisions beingdetected because of process variation. As such, more efficient, fasterexecution of the memory 14 may be facilitated. In this regard, theoverall efficiency and/or speed at which a computing environment may beexecuted may in turn be increased.

While various embodiments of the present invention have been describedin detail, it is apparent that further modifications and adaptations ofthe invention will occur to those skilled in the art. However, it is tobe expressly understood that such modifications and adaptations arewithin the spirit and scope of the present invention.

What is claimed is:
 1. An apparatus for collision detection in amultibank memory, comprising: a memory bank address comparator forreceiving bank address data corresponding to a first memory command anda second memory command, wherein the memory bank address comparator isoperable to output a bank match signal indicative of the first memorycommand and the second memory command being directed to a common memorybank address; a memory index address comparator for receiving indexaddress data corresponding to the first memory command and the secondmemory command, wherein the memory index address comparator is operableto output an index match signal indicative of the first memory commandand the second memory command being directed to a common memory indexaddress; and a collision detection circuit comprising a timingcorrection module that is operable to receive the bank match signal andthe index match signal and generate at least one of a corrected bankmatch signal or a corrected index match signal in response to a changedetected in one of the index match signal or bank match signalattributable to process variation; wherein the collision detectioncircuit is operable to compare the at least one of the corrected bankmatch signal or the corrected index match signal to generate a collisiondetection signal indicative of a collision in the multibank memoryresulting from the execution of the first memory command and the secondmemory command.
 2. An apparatus according to claim 1, wherein at leastone of the bank match signal or the index match signal includes processvariation resulting in an offset between the bank match signal and theindex match signal, and wherein the offset results in the falsedetection of a collision.
 3. An apparatus according to claim 2, whereinthe at least one of the corrected bank match signal or the correctedindex match signal reflects a state of a corresponding one of the bankmatch signal or the index match signal without the process variation. 4.An apparatus according to claim 3, wherein the process variation isdetected based on a comparison of at least two of the bank match signal,the corrected index match signal, the first memory command, and thesecond memory command.
 5. An apparatus according to claim 2, wherein theat least one of the corrected bank match signal or the corrected indexmatch signal is at least partially based on a change in a correspondingone of the index match signal or the bank match signal without detectionof a corresponding change in at least one of the first memory command,the second memory command or the other of the index match signal or bankmatch signal.
 6. An apparatus according to claim 5, wherein the changein the corresponding one of the index match signal or the bank matchsignal attributable to process variation is not reflected in the atleast one of the corrected bank match signal or the index match signal.7. An apparatus according to claim 2, wherein the offset results from atleast one of the bank match signal or the index match signal varyingfrom a first value to a second value without a corresponding variationin at least one of the first memory command, the second memory commandor the other of the index match signal or the bank match signal.
 8. Anapparatus according to claim 7, wherein the at least one corrected bankmatch signal or the corrected index match signal is different than acorresponding one of the bank match signal or the index match signal,respectively.
 9. An apparatus according to claim 8, wherein the indexmatch signal varies from the first value to the second value, andwherein the timing correction module is operable to maintain thecorrected index match signal at the first value at least until acorresponding change in at least one of the first memory command, thesecond memory command, or the other of the index match signal or thebank match signal.
 10. An apparatus according to claim 9, wherein thefirst memory command comprises a read command and the second memorycommand comprises a write command, and wherein the first memory commandand the second memory command result in a bypass condition.
 11. Anapparatus according to claim 1, wherein the execution of the firstmemory command and the second memory command is prevented in response tothe collision detection signal generated by the collision detectioncircuit.
 12. An apparatus according to claim 11, wherein the collisiondetection signal is communicated to the multibank memory.
 13. A methodfor detection of a collision, comprising: receiving a first memorycommand having an address comprising a first bank address and a firstindex address and a second memory command having an address comprising asecond bank address and a second index address; comparing the first bankaddress with the second bank address to generate a bank match signalindicative of whether the first bank address and the second bank addressare the same; evaluating the first index address with the second indexaddress to generate an index match signal indicative of whether thefirst index address and the second index address are the same; detectinga change in one of the bank match signal or the index match signalresulting from process variation; generating at least one of a correctedbank match signal or a corrected index match signal in response to thedetecting; and outputting a collision detection signal based on the atleast one of the corrected bank match signal or the corrected indexmatch signal.
 14. A method according to claim 13, wherein the generatingcomprises maintaining the corrected index match signal constant inresponse to a change in the index match signal so long as the bank matchsignal is constant.
 15. A method according to claim 14, wherein themaintaining is interrupted upon a change in the bank match signal.
 16. Amethod according to claim 15, wherein the maintaining is interrupted bya detected change in at least one of the first memory command or thesecond memory command.
 17. A method according to claim 16, wherein thecollision detection signal is indicative of a collision when acomparison of at least one of the corrected bank match signal or thecorrected index match signal indicates the first bank address and thesecond bank address are the same and the first index address and thesecond index address are different.
 18. A method according to claim 13,wherein the bank match signal and the index match signal indicate abypass condition prior to the change.
 19. A method according to claim13, further comprising preventing execution of the first memory commandand the second memory command when the collision detection signalindicates a collision.
 20. A system for collision detection relating toa multibank memory, comprising: a processor for generating a firstmemory command and a second memory command; a memory bank addresscomparator in operative communication with the processor for receivingbank address data corresponding to the first memory command and thesecond memory command, wherein the memory bank address comparator isoperable to output a bank match signal indicative of the first memorycommand and the second memory command being directed to a common memorybank address; a memory index address comparator in operativecommunication with the processor for receiving index address datacorresponding to the first memory command and the second memory command,wherein the memory index address comparator is operable to output anindex match signal indicative of the first memory command and the secondmemory command being directed to a common memory index address; and acollision detection circuit comprising a timing correction module thatis operable to receive the bank match signal and the index match signaland generate at least one of a corrected bank match signal or acorrected index match signal in response to a change detected in one ofthe index match signal or bank match signal attributable to processvariation; wherein the collision detection circuit is operable tocompare the at least one of the corrected bank match signal or thecorrected index match signal to generate a collision detection signalindicative of a collision in the multibank memory resulting from theexecution of the first memory command and the second memory command.